How a Machine Remembers - Latches, Clocks and Memory Cells

6.0 What this chapter gives you#

1. You will explain why a plain logic gate cannot remember anything.
2. You will draw an SR latch and say what all four input pairs do.
3. You will state the difference between a latch and a flip-flop in one line.
4. You will know setup time and hold time in picoseconds, and why breaking them causes metastability.
5. You will say why metastability can be made rare but never removed.
6. You will explain a clock tree, clock skew, jitter and clock gating.
7. You will build registers, shift registers and counters from flip-flops.
8. You will write a state machine as a table and a diagram, and see that a CPU control unit is one of these.
9. You will know how SRAM, DRAM and flash cells hold a bit, and why they cost such different amounts.
10. You will work out how many address lines a given capacity needs.

6.1 The problem: a gate forgets the moment its input changes#

PLAIN6.1.1 in simple words#

1. A logic gate looks at its inputs and drives an output, all the time.
2. Change an input and the output changes a moment later. Always.
3. So a gate has no past. It knows only what is on its wires right now.
4. A machine of gates alone therefore cannot remember.
5. The fix is short to say: wire the output back into the input.
6. Now the circuit tells itself what it was. That loop is feedback.
7. A good loop has two comfortable resting positions, one for 0 and one for 1. We call that bi-stable.

PLAIN6.1.2 a picture in your head#

1. Think of a light switch on a wall.
2. Your finger is the input. The switch position is the output.
3. Push it up, take your finger away, and it stays up.
4. A spring inside pushes it further whichever way it has started to move.
5. That spring is feedback. It will not sit halfway. Two positions only.

Where this comparison breaks:

1. A wall switch holds its position with no power. Our circuit needs power every second or it forgets.
2. A real switch can balance on the edge for a moment. So can a real memory circuit, and that matters a great deal (section 6.4).

PLAIN6.1.3 a worked example#

1. Take two NOT gates, each giving the opposite of its input.
2. Wire the first into the second, and the second back into the first.

        +---------------------------+
        |                           |
        v                           |
   A --[ NOT ]--> B --[ NOT ]--> A -+

   If A = 0 then B = 1 then A = 0.   Consistent. It holds.
   If A = 1 then B = 0 then A = 1.   Consistent. It holds.

3. Suppose A is 0. The first gate makes B equal 1, and the second makes A equal 0 again. Nothing moves.
4. Suppose A is 1. Then B is 0, which makes A equal 1. Again nothing moves.
5. Both answers are self-consistent, so that is one stored bit.
6. The bad news: no wire is left to say which bit to store. Section 6.2 fixes that.

PLAIN6.1.4 what is really happening inside#

1. Each NOT gate is a pair of transistors acting as a fast switch pair.
2. Input low connects the output to the supply. Input high connects it to ground.
3. In the loop, one gate always pulls up while the other pulls down.
4. A tiny voltage wobble from a nearby wire is amplified and pushed back round the loop, so the state survives noise.
5. There is a third position, in the middle, where both gates are half on.
6. In theory the loop can balance there. In practice it falls off in well under a nanosecond, because noise always exists.
7. The honest version: while settling, the loop is not digital at all. It is an analogue amplifier with its output tied to its input.

TECHNICAL6.1.5 the engineer’s version#

1. Two cross-coupled inverters form a bistable with two stable DC operating points and one metastable point between them.
2. Plotting one inverter’s voltage transfer curve against the other’s mirrored curve gives the butterfly plot, whose curves cross three times.
3. The largest square fitting inside a lobe is the static noise margin. For a 6T SRAM cell in a modern process, read noise margin is typically 100 to 200 mV at nominal supply, and collapses at low voltage.
4. Stability needs small-signal loop gain above 1 at the crossing point.
5. Recovery from the metastable point is exponential, with a time constant tau set by the loop gain-bandwidth product. Section 6.4 uses this.
6. The first electronic bistable was the Eccles-Jordan trigger circuit, built by William Eccles and Frank Jordan in 1918 from two vacuum triodes, published in the Radio Review in 1919, British patent 148,582.

WORDS6.1.6 remember these#

1. Feedback — sending an output back to an input — a closed signal loop whose gain can exceed unity.
2. Bi-stable — two comfortable resting states — a circuit with two stable DC operating points.
3. Metastable point — the wobbly middle — the unstable equilibrium between the two stable points.
4. Noise margin — how much interference a bit survives — static noise margin in millivolts, from the butterfly plot.
5. Volatile — forgets without power — state held only by current from the supply rail.

6.2 The SR latch from cross-coupled NOR gates#

PLAIN6.2.1 in simple words#

1. Our two-inverter loop could hold a bit but we could not write one.
2. A NOR gate outputs 1 only when all inputs are 0. Any input at 1 forces the output to 0.
3. Take two NOR gates and feed each one’s output into the other’s input.
4. The spare inputs are our controls: S for set, R for reset.
5. The outputs are Q and Q-bar, normally opposites.
6. Raise S and Q becomes 1. Raise R and Q becomes 0.
7. Put both back to 0 and the latch keeps what it had. That is remembering.
8. Raise both at once and it misbehaves. That case is called forbidden.

PLAIN6.2.2 a picture in your head#

1. Two people, each holding the other’s arm down. Whoever pushes down wins.
2. S is a referee who taps the first to make them stand. R taps the second.
3. With neither referee touching anyone, the pair stays as it was.
4. If both tap at once, both try to stand and nobody holds anybody down. The arrangement is broken while that lasts.
5. If both let go at the same instant, both lunge, and luck decides.

Where this comparison breaks:

1. People are slow and roughly equal. Gates differ by picoseconds, so the race is settled by manufacturing variation, not fairness.
2. People cannot stand half up for a measurable time. Gates can, and we call that metastability.

PLAIN6.2.3 a worked example#

1. All four cases of the NOR-based SR latch.

2. Case S=1, R=0. S forces one gate’s output to 0. The other then sees two zeroes and outputs 1. Q is 1, Q-bar is 0.
3. Case S=0, R=1 is the mirror image. Q becomes 0.
4. Case S=0, R=0 from Q=1. Each gate sees the other’s output holding it, so nothing moves.
5. Case S=1, R=1. Both gates have an input at 1, so both outputs go to 0. Q and Q-bar are now both 0, contradicting their names.
6. Drop both to 0 together and both gates try to output 1, then each sees the other’s 1 and tries to go back. The result is unpredictable.

PLAIN6.2.4 what is really happening inside#

1. Hold works because each output quietly holds the other gate’s input.
2. Set works because a 1 on S overpowers the feedback. A NOR gate with any input at 1 must output 0, whatever the feedback says.
3. The other gate then flips, reinforcing the first. A write is a short fight that the input wins, after which the loop locks in the winner.
4. The forbidden state is not magic. The outputs are simply no longer opposites, so anything reading Q-bar as “not Q” is being lied to.
5. The danger is leaving it. Both gates start identical and race, and the loser is decided by picoseconds.
6. The NAND version flips everything. A NAND outputs 0 only when all inputs are 1, so the controls are active low, written S-bar and R-bar.
7. For the NAND latch, S-bar=0 sets, R-bar=0 resets, both at 1 holds, and both at 0 is forbidden, driving both outputs to 1.

TECHNICAL6.2.5 the engineer’s version#

1. The NOR form is active-high on S and R. The NAND form is active-low.
2. The NAND form dominates in practice because a CMOS NAND is smaller and faster than a NOR of equal drive. That is a CMOS fact, not a logic rule.
3. Four NAND gates give the gated SR latch, and one more inverter gives the D latch of section 6.3.
4. The forbidden combination is precisely a non-complementary output condition, and the failure on release is a race condition decided by device mismatch and edge arrival order.
5. If the release edges are more than one loop delay apart, the last released loses, deterministically. Closer than that, the latch can go metastable.
6. The data sheet for the TTL part SN74LS279, a quad latch with active-low inputs, states it plainly: both inputs low is not a valid state.
7. In Verilog an always @* block with an incomplete if and no else infers a latch by accident. Synthesis warns about it, and the warning is almost always a real bug.

WORDS6.2.6 remember these#

1. SR latch — the simplest two-gate memory — a bistable set-reset element from cross-coupled NOR or NAND gates.
2. Set — store a 1 — drive Q high and let feedback hold it.
3. Hold — keep what is there — both controls inactive, feedback loop closed.
4. Forbidden state — the input pair you must not use — the non-complementary output condition, S=R=1 in the NOR form.
5. Race condition — two signals fighting to arrive first — an outcome decided by arrival time, not by logic values.
6. Active-low — does its job at 0 — asserted at logic low, written with a bar or a leading n, as in nRESET.

6.3 The gated D latch#

PLAIN6.3.1 in simple words#

1. The SR latch has two data inputs when we want one, and accepts changes at any moment.
2. The gated D latch fixes both. One data input, D. One control, enable.
3. When enable is 1, the latch copies D straight through to Q, following every move D makes.
4. When enable is 0, the latch stops looking and holds what it had.
5. Enable is a window. Open, data flows. Closed, the last value is trapped.
6. There is no forbidden input, because S and R now come from one D and can never both be 1.
7. The awkward part is the open window. While enabled the latch is see-through. That is transparency.

PLAIN6.3.2 a picture in your head#

1. A photocopier with a page sliding underneath it.
2. Enable is the shutter. While open, the copy keeps being redrawn as the page moves.
3. Close the shutter and the copy freezes at whatever was underneath then.
4. For a clean copy the page must be still while the shutter is open and for a moment after it closes.

Where this comparison breaks:

1. A smeared photocopy is obviously wrong. A latch that catches a value mid-change gives an ordinary-looking 0 or 1 that happens to be the wrong one. Nothing looks broken.

PLAIN6.3.3 a worked example#

1. A gated D latch over time. Time runs down the table.

2. At t1 enable is 0, so D is ignored and the old 0 stays.
3. From t2 to t4 enable is 1, and three changes of D give three changes of Q.
4. At t5 enable falls while D is 0, but Q keeps the value it had at the instant enable fell, which was 1.
5. Rows t2 to t4 are the problem. Q moved three times inside one enable pulse.

PLAIN6.3.4 what is really happening inside#

1. Build it from the NAND SR latch, which sets on S-bar=0 and resets on R-bar=0.
2. Put two steering gates in front. Feed D into one and NOT D into the other, and feed enable into both.
3. Enable at 0 makes both steering gates output 1, which is the NAND latch’s hold command. The latch is sealed.
4. Enable at 1 sends exactly one steering gate to 0, chosen by D. So D=1 sets and D=0 resets.
5. D and NOT D can never both be 1, so the forbidden case is unreachable. That is the real reason the D latch is safe.
6. Chain two transparent latches on the same enable and data can run through both in one pulse. Your two-stage pipeline silently becomes one stage.
7. The honest version: people say a latch “stores on the falling edge”. It does not. It stores continuously while enabled and merely stops at that edge.

TECHNICAL6.3.5 the engineer’s version#

1. The gated D latch is level-sensitive. Q is a function of D throughout the active level of the enable.
2. Its timing has setup and hold measured against the closing edge, plus D to Q delay while transparent and enable to Q delay at the opening edge.
3. In CMOS it is usually not gates but a transmission-gate latch: one pass gate into the storage node, one feedback inverter, one feedback pass gate.
4. That costs roughly 8 to 12 transistors against about 20 to 24 for an edge-triggered flip-flop, so latches are smaller and faster.
5. Latch-based pipelines allow time borrowing: a slow path can run past the nominal boundary into the next stage’s transparent window. Flip-flop pipelines cannot.
6. The cost is much harder static timing analysis, because tools must model transparency, borrowing limits and level-sensitive loops.
7. Standard cell libraries name these cells with D and L, as in DLH and DLL, meaning transparent when the enable is high or low.
8. Where experts disagree: whether latch-based design is worth it. Custom CPU teams say yes, for the area and the borrowing. Most ASIC and FPGA teams say no, because verification cost outweighs the gain.

WORDS6.3.6 remember these#

1. D latch — one data wire, one open-or-shut wire — a level-sensitive bistable whose output follows D while enabled.
2. Enable — the open-or-shut control — the level-sensitive gating signal, named EN, G or CLK.
3. Transparent — see-through — a live combinational path from D to Q during the active level.
4. Level-triggered — cares about the level, not the change — output is a function of D throughout the enable window.
5. Time borrowing — slow work spilling into the next stage — using transparency to absorb path delay past the nominal boundary.

6.4 The D flip-flop: edge-triggered memory#

PLAIN6.4.1 in simple words#

1. A latch is see-through while enabled, which is dangerous in a big machine.
2. We want something that takes one sample at one instant and then stops looking, however long the control stays high.
3. That is the D flip-flop, and it is edge-triggered.
4. Edge-triggered means it acts on the change of the clock, not on its level.
5. A rising-edge flip-flop copies D to Q the moment the clock goes 0 to 1, then ignores D until the next rising edge.
6. A flip-flop takes a photograph. A latch runs a video.
7. This makes it safe to wire one flip-flop’s output into the next one’s input, which is how every pipeline in every processor is built.
8. The price is that D must be steady just before the edge and just after it. Those are setup time and hold time.
9. Break them and the flip-flop can hesitate. That is metastability, and it can never be fully removed.

PLAIN6.4.2 a picture in your head#

1. A submarine airlock with two doors and one rule: both are never open.
2. Water enters the outer room while the outer door is open, but goes no further, because the inner door is shut.
3. The outer door shuts, the inner opens, and what is in the middle moves inward. Nothing new can follow it.
4. That is exactly a master-slave flip-flop. The master fills while the clock is low, the slave accepts while the clock is high.

Where this comparison breaks:

1. Airlock doors take a second. A flip-flop’s doors close in tens of picoseconds, and any overlap is what makes hold violations possible.
2. Water cannot be half in and half out. A voltage can.

PLAIN6.4.3 a worked example#

        +-----------+          +-----------+
  D --->| D       Q |-- Qm --->| D       Q |---> Q
        |  MASTER   |          |   SLAVE   |
        |  latch    |          |  latch    |
        |    EN     |          |    EN     |
        +-----+-----+          +-----+-----+
              |                      |
            [NOT]                    |
              |                      |
  CLK --------+----------------------+

  CLK = 0 : master transparent, slave holding
  CLK = 1 : master holding,     slave transparent

1. Clock at 0. The master is transparent so Qm follows D. The slave is shut, so Q does not move.
2. Clock rises. The master seals, trapping the last value of D. The slave opens and passes that trapped value to Q.
3. Change D while the clock is still 1. The master is shut, so nothing happens.
4. Clock falls. The slave seals, keeping Q, and the master opens again to track the new D for the next edge.
5. So Q changes exactly once per cycle, at the rising edge.
6. That is the race edge-triggering solves. With plain latches a value could travel through three stages in one enable pulse, skipping two cycles of work. With flip-flops one edge moves data exactly one stage.

PLAIN6.4.4 what is really happening inside#

1. Setup time is how long D must already be steady before the edge arrives.
2. Hold time is how long D must stay steady after it.
3. Together they define a small forbidden window in which D may not change.
4. The reason is physical. The master is closing a switch and handing over to a feedback loop, and that handover needs a firm push one way.
5. If D moves as the switch closes, the loop starts near the middle, where neither 0 nor 1 is winning.
6. It still recovers, because the middle is unstable, but recovery takes an unpredictable time.
7. Occasionally the next stage samples a half-formed voltage, and two different stages can then read the same wire as 0 and as 1.
8. The chance drops exponentially with the extra settling time you allow, but it never reaches zero.
9. The fix is a synchronizer: two or three flip-flops in a row on the same clock, whose only job is to buy the first one extra clock periods.

TECHNICAL6.4.5 the engineer’s version#

1. A positive-edge-triggered D flip-flop samples D in an aperture defined by setup time t-su and hold time t-h, and drives Q after clock-to-output delay t-cq.

2. The 74LS74 figures are from the Fairchild and Texas Instruments data sheets at 5 V, 25 degrees Celsius and a 15 pF load. The 7 nm figures are typical orders of magnitude, since vendor libraries are confidential.
3. Static timing analysis checks two inequalities on every path. Setup: t-cq + t-logic + t-skew <= T-clk - t-su. Hold: t-cq + t-logic >= t-h + t-skew.
4. Setup failures are fixed by slowing the clock. Hold failures are not, and must be fixed by adding delay in silicon.
5. Metastability resolution is exponential in the settling time available:

   MTBF = exp(t_r / tau) / (T0 * f_clk * f_data)

   t_r    = settling time available after the sampling edge
   tau    = resolution time constant of the flip-flop
   T0     = effective width of the metastable aperture
   f_clk  = sampling clock frequency
   f_data = rate at which the asynchronous input changes

6. Worked example at a deliberately pessimistic slow corner, with tau = 50 ps, T0 = 1 ps, f_clk = 1 GHz and f_data = 10 MHz:

7. One extra flip-flop moved the answer eight orders of magnitude, because the exponential dominates everything else.
8. Two-flop synchronizers are the convention for single-bit control signals crossing clock domains. Three are used at very high frequency or in safety-critical logic.
9. A synchronizer handles one bit. Multi-bit values crossing domains need Gray coding, a handshake or an asynchronous FIFO, because independently synchronized bits can resolve on different cycles.
10. Thomas Chaney and Charles Molnar documented this in their 1973 IEEE Transactions on Computers paper on anomalous synchronizer behaviour, and Leslie Lamport gave the impossibility argument in his 1984 note on Buridan’s principle.
11. Established fact: no purely digital circuit can eliminate metastability. Marketing claim: any product described as metastability-proof. What such products mean is a very long MTBF.
12. Tools that observe this: report_timing in Synopsys PrimeTime or Cadence Tempus, and clock-domain-crossing checkers such as SpyGlass CDC.

WORDS6.4.6 remember these#

1. Flip-flop — memory sampling once per clock edge — an edge-triggered bistable, usually master-slave.
2. Setup time — data ready before the edge — minimum stable interval before the clock edge, t-su.
3. Hold time — data steady after the edge — minimum stable interval after the clock edge, t-h.
4. Metastability — hesitating between 0 and 1 — an output resting near the unstable equilibrium for an unbounded time.
5. MTBF — average time between rare failures — mean time between failures, exponential in available settling time.
6. Synchronizer — flip-flops that buy settling time — a chain of same-clock registers at a clock domain crossing.

6.5 The clock: why the whole chip marches in step#

PLAIN6.5.1 in simple words#

1. A clock is a wire carrying a signal that goes 0, 1, 0, 1 at a steady rate.
2. Drawn on paper it looks like a row of blocks, so we call it a square wave.
3. The moment it goes from 0 to 1 is the rising edge, when most flip-flops act.
4. Every flip-flop shares the same clock, so on each edge the whole machine takes one step together.
5. Between edges the gates that compute work out the answers for the next step.
6. The period must be long enough for the slowest of those. That is what limits speed.
7. One billion ticks per second is 1 GHz, so each tick lasts one nanosecond.

PLAIN6.5.2 a picture in your head#

1. A large rowing boat with many rowers and one drum.
2. The drum beats and every rower pulls once. Nobody watches anyone else.
3. The beat cannot be faster than the slowest rower’s stroke.
4. If the sound reaches the back later than the front, the margin shrinks. That difference is clock skew.
5. If the drummer is slightly irregular, that is jitter.
6. If some rowers rest, stop sending them the beat. That is clock gating.

Where this comparison breaks:

1. Rowers hear one drum. On a chip the clock must be copied through thousands of buffers to reach millions of flip-flops, and every copy adds delay and its own irregularity.

PLAIN6.5.3 a worked example#

1. A 3 GHz clock has a period of 0.333 nanoseconds, which is 333 picoseconds.
2. Say clock-to-Q is 30 ps and the next flip-flop needs 25 ps of setup. That leaves 278 ps for all the logic.
3. Allow 20 ps of skew and 10 ps of jitter and the logic has 248 ps.
4. At roughly 15 ps per gate stage, that is about 16 gate delays per cycle.
5. Roughly 15 to 20 gate delays per cycle has been near constant in processor design for two decades, whatever the frequency.

   PLL --> [trunk buffer]
                 |
        +--------+--------+
        |                 |
    [buffer]          [buffer]
      /   \             /   \
  [buf]  [buf]      [buf]  [buf]
   / \    / \        / \    / \
  FF FF  FF FF      FF FF  FF FF

6. The aim of that tree is that every path from trunk to leaf is the same length, so all flip-flops see the edge at the same time.

PLAIN6.5.4 what is really happening inside#

1. The clock starts as a wobbling sine wave from a quartz crystal, typically 24 or 25 MHz on a modern board.
2. A phase-locked loop multiplies it up to the frequency the chip needs and squares it off.
3. That is driven into the trunk and copied outwards by buffers, roughly doubling at each level.
4. Every buffer costs delay and power. The clock network alone commonly burns 20 to 40 per cent of a high-performance chip’s dynamic power.
5. Clock gating puts an AND gate in front of a branch and switches off the beat to a block with nothing to do, saving flip-flop and buffer power together.
6. Skew is not always bad. Deliberately delaying one leaf, called useful skew, lends time from one pipeline stage to a slower one.
7. The honest version: a real clock edge is not vertical. It rises over tens of picoseconds, and every flip-flop decides somewhere on that slope.

TECHNICAL6.5.5 the engineer’s version#

1. Period T is 1 divided by frequency: 1 GHz gives 1000 ps, 3 GHz gives 333 ps, 5 GHz gives 200 ps.
2. Desktop parts now pass 6 GHz. The Intel Core i9-14900KS, launched in March 2024, was specified at 6.2 GHz maximum turbo.
3. Skew is the arrival-time difference between two flip-flops. Common sign-off targets keep global skew under about 5 per cent of the period.
4. Jitter splits into period, cycle-to-cycle and long-term jitter. A few picoseconds RMS is typical for an on-chip PLL.
5. Skew helps or hurts by direction. Positive skew from launch to capture relaxes setup and tightens hold, which is why hold violations often appear only after clock tree synthesis.
6. Distribution styles are the balanced H-tree, the buffered fishbone and the full clock mesh. Grids give the lowest skew and cost the most power, and IBM POWER designs used them.
7. Clock gating is inserted as integrated clock-gating cells, usually inferred by synthesis from an enabled register description. Power gating is different: it removes the supply, and loses state without retention cells.
8. Asynchronous design drops the global clock for local handshakes. It works and stays a niche. The Amulet processors at the University of Manchester in the 1990s were asynchronous implementations of the ARM architecture.
9. Tools that observe this: report_clock_timing -type skew in PrimeTime, and cpupower frequency-info on Linux for the current core clock.

WORDS6.5.6 remember these#

1. Clock — the steady tick everything follows — a periodic square wave whose active edge triggers all synchronous elements.
2. Rising edge — the moment the tick goes up — the low-to-high transition, the sampling instant for a positive-edge flip-flop.
3. Clock skew — the tick arriving at different times — the spatial difference in clock arrival between two sequential elements.
4. Jitter — the tick being slightly irregular — temporal variation of edge position, in RMS or peak-to-peak picoseconds.
5. Clock tree — the branching wiring that copies the clock — the buffered distribution network from source to every leaf register.
6. Clock gating — switching the tick off to idle parts — inserting an enable into the clock path to save dynamic power.

6.6 Registers, shift registers and counters#

PLAIN6.6.1 in simple words#

1. One flip-flop holds one bit. For a byte, use eight side by side on the same clock. That group is a register.
2. A 32-bit register is 32 flip-flops. A CPU’s small set of named working registers is the register file.
3. Pass each flip-flop’s output to its neighbour instead and you get a shift register, whose whole row slides one place each edge.
4. A shift register turns one wire into a row of bits, one bit per tick. That is how a slow single-wire link becomes a parallel byte.
5. A counter is a register that adds one to itself on every clock edge.
6. Counters measure time, address memory, count events and divide clocks.

PLAIN6.6.2 a picture in your head#

1. A row of eight boxes on a belt, each holding a black or white marble.
2. A register is the belt stopping and all eight boxes being refilled at once from eight chutes above.
3. A shift register is the belt moving one box right each tick, a new marble dropping in at the left and the rightmost falling off.
4. Feed one marble per tick, wait eight ticks, and a full byte is lined up. That is serial-to-parallel conversion.
5. A counter is a row of odometer wheels, the rightmost turning every tick and nudging its neighbour when it passes nine.

Where this comparison breaks:

1. On an odometer the nudge travels wheel by wheel, taking time. That is a ripple counter, the slow kind.
2. A good digital counter computes every digit in parallel and changes them all on one edge. That is a synchronous counter.

PLAIN6.6.3 a worked example#

1. A 4-bit synchronous up counter, one row per clock edge.

2. Q0 changes every tick, so its frequency is half the clock. Q1 changes every second tick, so its frequency is a quarter.
3. A 4-bit counter is therefore also a divide-by-2, 4, 8 and 16 circuit, free.
4. The rule for each bit: bit n flips when all the bits below it are 1.
5. At tick 16 it rolls over. Four bits count only to 15, and wrapping is not an error, it is arithmetic modulo 16.

PLAIN6.6.4 what is really happening inside#

1. In a synchronous counter every flip-flop shares the clock, with a little logic in front computing its next value.
2. For bit 0 that logic is “the opposite of what I am”. For bit 1 it is “flip me if bit 0 is 1”, and so on up the chain.
3. All of those run in parallel during the clock period, and at the edge all bits update together.
4. In a ripple counter only bit 0 sees the real clock. Bit 1 is clocked by bit 0’s output, bit 2 by bit 1’s, and so on.
5. That is cheaper in gates, but the change travels along the chain, so the top bit updates several gate delays after the bottom.
6. Going from 7 to 8, a 4-bit ripple counter can briefly show 6, then 4, then 0. Anything sampling it then reads a lie.
7. A shift register is simpler still. Each flip-flop’s D input is the previous flip-flop’s Q output, with no logic in between.

TECHNICAL6.6.5 the engineer’s version#

1. A register is an n-bit array of edge-triggered flip-flops sharing a clock, and usually a reset and a load enable.
2. A register file is a small multi-ported array. A 64-bit RISC core has 32 architectural integer registers, and a 4-wide machine may need 8 read and 4 write ports, which is why register files use custom SRAM-like cells rather than standard flip-flops.
3. Shift registers are classed by interface: SISO, SIPO, PISO and PIPO, for serial or parallel in and out.
4. Real parts: the 74HC595 is an 8-bit serial-in, parallel-out shift register with an output latch, widely used to drive LED arrays from three microcontroller pins. The 74HC165 is its parallel-in, serial-out partner.
5. Serial-to-parallel conversion by shift register is how SPI, JTAG boundary scan and many display drivers work.
6. A linear feedback shift register feeds an exclusive-OR of chosen taps back to the input. A maximal-length n-bit LFSR cycles through all 2 to the power n, minus 1, non-zero states, and is used for test patterns and for scrambling in Ethernet and PCI Express.
7. Ripple counters cost the fewest gates but glitch and are limited by the chain delay. Synchronous counters cost more logic, never glitch at the outputs, and are limited only by one stage.
8. A synchronous counter in Verilog is four lines:

always @(posedge clk) begin
  if (rst)      count <= 4'd0;
  else if (en)  count <= count + 4'd1;
end

9. Tools that observe this: perf stat on Linux reads hardware performance counters, which are wide synchronous counters inside the CPU, and rdtsc on x86 reads the time-stamp counter.

WORDS6.6.6 remember these#

1. Register — a row of flip-flops holding a number — an n-bit array of edge-triggered elements on a common clock.
2. Register file — the CPU’s small set of named boxes — a multi-ported array of architectural registers with dedicated ports.
3. Shift register — bits sliding one place per tick — a chain of flip-flops with Q of one feeding D of the next.
4. Ripple counter — digits nudging each other along — an asynchronous counter where each stage clocks the next.
5. Synchronous counter — all digits changing together — next-state logic on a shared clock, so all bits settle on one edge.
6. LFSR — a shift register with a feedback trick that looks random — a linear feedback shift register giving a pseudo-random sequence.

6.7 Finite state machines#

PLAIN6.7.1 in simple words#

1. A machine with memory can be in different situations. Each is a state.
2. A finite state machine has a fixed list of states and rules for moving between them.
3. A rule says: in this state, seeing this input, move to that state on the next clock tick.
4. It also produces outputs, which are the things it makes happen.
5. Three pieces build one: a register holding the state, logic computing the next state, and logic computing the outputs.
6. If outputs depend only on the state, it is a Moore machine.
7. If they depend on the state and the current inputs, it is a Mealy machine. Moore outputs are steadier, Mealy machines need fewer states.

PLAIN6.7.2 a picture in your head#

1. A board game where you move one token between numbered squares.
2. The token’s square is the state, and there is only one token.
3. The painted arrows are the transitions, each with a condition written on it.
4. The clock is the drum from section 6.5. Between beats you decide, on the beat you move.
5. Squares with an instruction printed on them, like “turn the green lamp on”, give Moore outputs. Arrows with an instruction, like “ring the bell as you pass”, give Mealy outputs.

Where this comparison breaks:

1. In a board game you can pause and think. A real state machine must have its next state fully computed before the next clock edge, every time.

PLAIN6.7.3 a worked example#

1. A traffic light for one direction, with one input T meaning the countdown timer has finished.

   +--------> S0 RED ---------+
   |           (5 s)          |
   |             |            |
   |           T = 1          |
   |             v            |
   |       S1 RED + AMBER     |
   |           (2 s)          |
   |             |            |
   |           T = 1          |
   |             v            |
 T = 1       S2 GREEN         |
   |           (5 s)          |
   |             |            |
   |           T = 1          |
   |             v            |
   +-------- S3 AMBER <-------+
              (2 s)

2. The state table, with the lamps written R, A and G.

3. This is a Moore machine. In the last column the lamps depend only on the state, never on T.
4. Four states need two bits, so the state register is two flip-flops, with S0 = 00, S1 = 01, S2 = 10 and S3 = 11.
5. To make it Mealy, add an output firing only during a move, such as a pulse reloading the timer. That pulse depends on the state and on T being 1.

always @(posedge clk)
  if (rst) state <= S0;
  else case (state)
    S0: state <= T ? S1 : S0;
    S1: state <= T ? S2 : S1;
    S2: state <= T ? S3 : S2;
    S3: state <= T ? S0 : S3;
  endcase

PLAIN6.7.4 what is really happening inside#

1. On each clock edge the state register captures whatever the next-state logic worked out during the previous period.
2. The next-state logic is pure gates, seeing the current state bits and the inputs and producing the next state bits.
3. The output logic is pure gates too, and in a Moore machine it sees only the state bits.
4. So the loop is: state register drives logic, logic drives state register, clock decides when it advances. Nothing else.
5. A Moore output cannot react to an input in the same cycle. That one-tick delay is the price of its stability.
6. Now the big claim. A CPU’s control unit is exactly this structure and nothing more.
7. Its state includes where it is in the instruction cycle. Its inputs include decoded instruction bits, flags and interrupt lines. Its outputs are the control wires that open registers, pick an ALU operation and start a memory access.
8. The only difference from our traffic light is size: four states here, hundreds across dozens of units in an out-of-order core.
9. The honest version: a modern CPU is not one giant state machine. It is many communicating state machines, plus large regular structures such as caches and queues that nobody describes state by state.

TECHNICAL6.7.5 the engineer’s version#

1. Formally an FSM is a state set, an input alphabet, an output alphabet, a transition function, an output function and an initial state.
2. Any Mealy machine converts to a Moore machine, usually at the cost of more states.
3. Encoding matters in silicon. Binary uses the fewest flip-flops, 3 bits for 8 states. One-hot uses 8, but gives the simplest next-state logic. Gray uses 3 and changes only one bit per step.
4. One-hot is the convention in FPGA design, where flip-flops are plentiful and wide logic is expensive. Binary is more common in ASICs, where flip-flop area is the cost.
5. Gray encoding is used where state bits cross a clock domain, because only one bit changes per transition, so only one bit can be sampled ambiguously. That is standard inside asynchronous FIFOs.
6. Illegal states must be handled. Safety-related designs use a full default branch forcing a return to a known state, so a single-event upset cannot wedge the machine.
7. Maurice Wilkes proposed microprogramming in 1951, holding the control unit’s transitions in a small read-only memory rather than in fixed gates. IBM used it heavily in System/360 from 1964, which is how one architecture ran on very different hardware.
8. Modern x86 processors still contain microcode, which is why microcode updates can change processor behaviour after manufacture. That is how the 2018 Spectre and Meltdown mitigations reached shipped chips.
9. Tools that observe this: yosys -p 'fsm_detect; fsm_map' reports inferred state machines, and commercial synthesis lists the encodings it chose.

WORDS6.7.6 remember these#

1. State — the situation the machine is in — one value held in the state register, from a finite set.
2. Transition — the move from one situation to another — the next-state function evaluated at a clock edge.
3. Moore machine — outputs depend on where you are — output is a function of the current state alone.
4. Mealy machine — outputs depend on where you are and what you see — output is a function of state and inputs.
5. One-hot — one flip-flop per state, only one set — an encoding of Hamming weight 1, favoured in FPGAs.
6. Microcode — the control unit’s own tiny program — a stored microprogram in ROM or writable control store sequencing control signals.

6.8 SRAM: the six-transistor cell#

PLAIN6.8.1 in simple words#

1. SRAM means static random access memory. Static means it holds its value while power is on, with no help.
2. One cell is the two-inverter loop of section 6.1 plus two switches that let us reach inside.
3. Each inverter is two transistors, and the two switches make six. Hence the name, the six-transistor cell.
4. Both switches are opened by one wire, the word line.
5. Outside are two wires, the bit lines, one carrying the value and one its opposite.
6. To read, open the word line and let the cell tip the bit lines slightly apart. An amplifier notices which way.
7. To write, drive the bit lines hard and open the word line. The drivers overpower the loop and flip it.
8. SRAM is fast because the answer is already sitting there, and expensive because six transistors per bit is a lot of silicon.

PLAIN6.8.2 a picture in your head#

1. A see-saw with a child sitting firmly on one end.
2. Reading is feeling which end is down, without changing it.
3. Writing is an adult pushing the high end down until it settles the other way.
4. It never needs topping up. While gravity works, it stays.
5. But a see-saw takes a lot of space, and only a few fit in the playground.

Where this comparison breaks:

1. Gravity is free. An SRAM cell’s gravity is a small current from the supply running for ever, and across a large cache that leakage is a real part of a chip’s idle power.

PLAIN6.8.3 a worked example#

        Vdd            Vdd
         |              |
       [ P1 ]         [ P2 ]
         |              |
  BL --[M5]--o A      B o--[M6]-- BLbar
         |              |
       [ N1 ]         [ N2 ]
         |              |
        GND            GND

  WL, the word line, drives the gates of M5 and M6.
  Node A drives the gates of P2 and N2.
  Node B drives the gates of P1 and N1.
  P1 with N1 is one inverter. P2 with N2 is the other.

1. To store a 1, node A is high and node B is low. P1 holds A up, N2 holds B down, and each keeps the other in place.
2. To read, first charge both bit lines to the supply and let go. That is precharging.
3. Raise the word line. B is low, so the cell pulls BLbar down through M6 and N2, while BL stays high.
4. After a short time the bit lines differ by about 50 to 100 millivolts, and a sense amplifier drives that difference out at full logic level.
5. To write a 0, drive BL to ground and BLbar to the supply, then raise the word line. The external drivers beat the cell and node A is dragged down.
6. Sizing is the whole art. M5 and M6 must be weak enough not to disturb the cell on a read, yet the write drivers must still beat P1 and P2.

PLAIN6.8.4 what is really happening inside#

1. A cache is a rectangular array of millions of these cells, sharing word lines along rows and bit lines down columns.
2. Only one word line is raised at a time, which selects one row.
3. Every column in that row dumps its value onto its own bit line pair at once, so a whole row is read in parallel, and column select logic then picks the bits you asked for.
4. SRAM is fast because the sequence is short: decode, raise a word line, let the bit lines separate a little, amplify, output.
5. There is no waiting for a capacitor to fill and no restoring afterwards, because reading did not destroy anything.
6. The honest version: reading does disturb the cell slightly. The read current lifts the low node, and in a weak cell or at low supply that can flip the bit. This is read upset, and it is why SRAM fails at low voltage before ordinary logic does.

TECHNICAL6.8.5 the engineer’s version#

1. The standard cell is 6T. An 8T cell adds a separate read port to remove read disturb, and 10T cells are used at very low voltage.
2. Published high-density 6T bitcell areas:

3. Sources quote TSMC N5 as either 0.021 or 0.0199 square micrometres depending on the cell variant. The fact to keep is that SRAM barely shrank from 5 nm to 3 nm and shrank again at 2 nm.
4. Cost estimate, since SRAM is never sold by the gigabyte. A gigabyte is about 8.6 thousand million bits, so at 0.021 square micrometres per bit that is roughly 180 square millimetres of bitcell, or about 300 once decoders, sense amplifiers and error correction are added.
5. A 300 mm wafer holds about 70 700 square millimetres, and leading-edge wafer prices are publicly estimated at 16 000 to 20 000 US dollars. That puts SRAM near 100 to 200 US dollars per gigabyte, as an order of magnitude only.
6. Typical latencies in a current core, roughly 1 ns, 4 ns and 12 ns at 4 GHz:

7. The Intel 3101, released in 1969, was Intel’s first product: a 64-bit bipolar SRAM. The Intel 1101 of the same year was a 256-bit MOS SRAM.
8. SRAM leakage is dominated by subthreshold and gate leakage and scales badly, so designs use multiple threshold voltages and array power gating.
9. Tools that observe this: lscpu and getconf -a | grep CACHE print cache sizes, and perf stat -e cache-misses counts misses against them.

WORDS6.8.6 remember these#

1. SRAM — memory that holds itself up while powered — static RAM built from cross-coupled inverter cells.
2. 6T cell — the six-transistor bit — two inverters plus two access transistors sharing one word line.
3. Word line — the wire that selects a row — the row line driving the gates of the access transistors.
4. Bit line — the wire carrying the value in and out — one of a complementary pair, precharged before each read.
5. Sense amplifier — hears a whisper and shouts it — a differential amplifier resolving a small bit line split into full logic.
6. Read upset — a read accidentally changing the bit — a cell flip caused by read current lifting the storage node.

6.9 DRAM: one transistor and one capacitor#

PLAIN6.9.1 in simple words#

1. DRAM means dynamic random access memory. Dynamic means it does not hold itself up and must be topped up constantly.
2. One cell is a single transistor acting as a switch, plus a tiny capacitor, which is a bucket for charge.
3. Charge in the bucket means 1. An empty bucket means 0.
4. Two components instead of six is why DRAM is so much cheaper and denser than SRAM. That is the entire reason it exists.
5. The bucket leaks, and left alone it empties in a fraction of a second.
6. So the chip walks through every row, reads it and writes it straight back. That is refresh, and it never stops while power is on.
7. Worse, reading a cell empties the bucket, so every read is automatically followed by a write-back of what was found.

PLAIN6.9.2 a picture in your head#

1. A wall of thousands of small buckets, each with a slow drip.
2. In under a tenth of a second a full bucket becomes ambiguous.
3. A worker walks the wall topping up every bucket that still looks full, and must get round before the first goes bad. That deadline is the refresh interval.
4. Checking a bucket means tipping it into a measuring tray, so you must then pour it back.
5. The tray starts half full, so a bucket tips it slightly up or down. That tiny difference is what the sense amplifier measures.

Where this comparison breaks:

1. Water can be at any level. A cell that has half leaked is not half a bit, it is a bit the sense amplifier will read wrongly. No partial credit.

PLAIN6.9.3 a worked example#

1. A modern DRAM cell capacitor is around 6 to 10 femtofarads and the supply is about 1.1 volts.
2. Charge equals capacitance times voltage, so 10 femtofarads times 1.1 volts is 11 femtocoulombs.
3. Dividing by the charge on one electron gives roughly 69 000 electrons for a stored 1. That is the whole physical difference between 1 and 0 in your main memory.
4. Now the refresh arithmetic for DDR4. The standard refresh window is 64 milliseconds up to 85 degrees Celsius.
5. A DDR4 device needs 8192 refresh commands to cover everything, so one command must go out on average every 64 divided by 8192 milliseconds, which is 7.8 microseconds. That figure is tREFI.
6. Above 85 degrees the window halves to 32 milliseconds and tREFI halves to 3.9 microseconds.
7. DDR5 tightened this. Its normal window is 32 milliseconds up to 85 degrees, giving a tREFI of 3.9 microseconds, and 16 milliseconds from 85 to 95.
8. So the familiar answer of 64 milliseconds is right for DDR through DDR4 and out of date for DDR5. Both figures are in the JEDEC standards.

PLAIN6.9.4 what is really happening inside#

1. Cells sit in a grid. A row is selected by a word line, a column is read out on a bit line.
2. Precharge. Every bit line is driven to exactly halfway between supply and ground, then left floating.
3. Activate. The chosen word line rises, connecting every cell in that row to its bit line.
4. The cell’s tiny charge tips the much larger bit line by tens of millivolts, and the cell is now drained. That is the destructive read.
5. Sense. The sense amplifier is a cross-coupled pair, exactly like section 6.1, which latches onto whichever side is higher and drives the pair fully apart.
6. That same act refills the cell through the still-open word line, so the write-back is automatic and free.
7. The whole row now sits in the sense amplifiers, together called the row buffer, typically 1 or 2 kilobytes.
8. Column select. Only now do we pick the bytes we asked for and send them off the chip.
9. Another request in the same row skips straight to that last step. That is a row buffer hit, and it is much faster. A different row means precharging and activating again.
10. Because the address arrives in two halves, the control signals are called RAS, row address strobe, and CAS, column address strobe. The names are from the 1970s and the signals still exist.

TECHNICAL6.9.5 the engineer’s version#

1. Robert Dennard invented the one-transistor, one-capacitor cell at IBM’s Thomas J. Watson Research Center in 1966, filed in 1967, and was granted United States patent 3,387,286 in 1968.
2. The Intel 1103, launched in October 1970, was a 1 kilobit PMOS DRAM and the first commercially successful one. It ended magnetic core memory.
3. Address multiplexing latches the row address on the falling edge of RAS and the column address on the falling edge of CAS. This halved the pin count, and is why the terms survive in modern timing parameters.
4. The four numbers on any memory module label:

5. A row buffer hit costs CL alone. A row conflict costs tRP plus tRCD plus CL. At DDR5-6400 those are about 12.5 ns and about 37 ns, before queueing.
6. Above the cell: cells form subarrays, subarrays form banks, banks form bank groups, chips accessed together form a rank, and a controller port is a channel. DDR5 splits each DIMM into two 32-bit sub-channels.
7. Banks let the controller keep several rows open and overlap activation with data transfer, which is where most real bandwidth comes from.
8. The DDR family, with JEDEC publication years:

9. DDR4 parts reached the market in 2014, two years after the standard. DDR5 was published on 14 July 2020, and JEDEC raised its ceiling to 8800 MT/s in an update published in April 2024 that also added anti-rowhammer features.
10. DDR6 is in development. Reporting through 2025 and 2026 points to a 2027 timeframe and an 8800 to 17 600 MT/s range. No standard is published yet, so treat that as expectation, not fact.
11. Now the point of the section. DDR-400 at CL3 in 2000 gave a CAS latency of 15 ns and 3.2 GB/s per 64-bit module. DDR5-6400 at CL40 gives 12.5 ns and 51.2 GB/s. Bandwidth rose sixteenfold, latency improved about twenty per cent, in twenty-five years.
12. The reason is physics, not laziness. Bandwidth is bought with more banks, wider buses and faster signalling. Latency is set by charging a long, heavy bit line through one small transistor, and that has not changed.
13. DDR5 added a same-bank refresh command, REFsb, beside the all-bank REFab. For a 16 Gb device Micron quotes tRFC of 295 ns for REFab and 130 ns for REFsb, and reports 6 to 9 per cent throughput gain from using REFsb.
14. Every DDR5 chip carries on-die ECC, 8 parity bits over 128 data bits. That covers internal cell errors and is not the same as module-level ECC.
15. Tools that observe this: dmidecode -t memory prints module type, speed and rank, and Intel MLC measures achieved bandwidth and idle latency.

WORDS6.9.6 remember these#

1. DRAM — memory that must be topped up — dynamic RAM using a one-transistor, one-capacitor cell.
2. Refresh — the constant topping up — periodic read and restore of every row inside the retention window, paced by tREFI.
3. Destructive read — looking at it empties it — charge sharing from cell to bit line, requiring an automatic restore.
4. Row buffer — the row currently held open — the sense amplifier array holding one activated row, typically 1 to 2 kilobytes.
5. RAS and CAS — the two halves of an address — row address strobe and column address strobe, from multiplexed addressing.
6. Bank — an independently openable section — a subarray group with its own row buffer, allowing overlapped access.
7. Rank — a set of chips answering together — devices on a module selected by one chip select and sharing the data bus.
8. Channel — one road between controller and memory — an independent memory controller port with its own command and data buses.

6.10 Non-volatile cells: from mask ROM to flash#

PLAIN6.10.1 in simple words#

1. Everything so far forgets when power goes. Now we want cells that remember without it.
2. Mask ROM has the bits built in during manufacture by the shape of one layer. It can never be changed.
3. PROM leaves the factory blank with a tiny fuse at every bit. You blow selected fuses with current, once, and a blown fuse cannot be repaired.
4. EPROM stores charge instead of blowing metal. Its package has a quartz window: shine ultraviolet light through it for about twenty minutes and every bit returns to blank.
5. EEPROM does the same erase with voltage rather than light, one byte at a time.
6. Flash is EEPROM that erases in large blocks instead of by byte. That one restriction made it far smaller and far cheaper.
7. All three of the last ones store a bit as electrons trapped on a small island of conductor with no wires attached to it.

PLAIN6.10.2 a picture in your head#

1. A hollow in the top of a hill, ringed by a high ridge, with no path in.
2. Marbles in the hollow are the trapped electrons, and present or absent is the stored bit.
3. Nothing takes them out, because the ridge is too high. They sit for years.
4. To put marbles in you either fire them hard enough to fly over the ridge, which is hot-electron injection, or tilt the hill steeply so they slip across a thin part, which is tunnelling.
5. To read you notice that the hill’s shape is slightly different when the pile is there.
6. Every firing chips rock off the ridge, and after enough thousands of times marbles leak out on their own. That is wear.

Where this comparison breaks:

1. Marbles are in or out. Electrons are quantum objects and tunnelling is a probability, not a rolling motion. The ridge is an energy barrier of roughly 3.2 electron volts between silicon and silicon dioxide.

PLAIN6.10.3 a worked example#

        control gate
   =========================
        oxide layer
   -------------------------
        floating gate           <- charge lives here
   -------------------------
        tunnel oxide, 8 to 10 nm thick
   =========================
    source |  channel  | drain
   =========================
             substrate

1. A floating-gate transistor is an ordinary transistor with a second gate buried in the insulator, connected to nothing.
2. With no electrons on it, a moderate voltage on the control gate switches the transistor on. Call that erased.
3. Trap electrons there and their negative charge repels the control gate’s influence, so the same voltage no longer switches it on. Call that programmed.
4. Reading is applying a fixed voltage and seeing whether current flows. The threshold has shifted, typically by two to four volts in older parts.
5. Control the charge finely and you get several distinct levels, and so more than one bit per cell.

PLAIN6.10.4 what is really happening inside#

1. NOR flash programs by channel hot-electron injection: a large voltage across the channel accelerates electrons until some jump the barrier.
2. That is fast per byte but draws heavy current, so it cannot be done to many cells at once.
3. NAND flash uses Fowler-Nordheim tunnelling for both writing and erasing. A high field across a very thin oxide lets electrons tunnel through.
4. Tunnelling draws almost no current, so thousands of cells can be programmed together. That is exactly why NAND is used for bulk storage and NOR is not.
5. The 15 to 20 volts needed are made on the chip by charge pumps, from an ordinary 3.3 volt supply.
6. Erase pulls electrons back off, and only a whole block at a time, typically several megabytes.
7. That block-erase rule causes nearly everything odd about SSDs. You cannot overwrite in place, so you write elsewhere, remember where, and collect the garbage later.
8. Retention comes from the barrier height, so it is always quoted with a temperature, because heat helps electrons escape.
9. The honest version: most flash sold today is not floating-gate at all. Modern 3D NAND mostly uses charge trap cells, where electrons sit in a layer of silicon nitride full of defects rather than on a conductive island.

TECHNICAL6.10.5 the engineer’s version#

1. The floating-gate MOSFET was invented by Dawon Kahng and Simon Sze at Bell Labs in 1967.
2. Dov Frohman at Intel turned it into a product. The Intel 1702 of 1971 was the first EPROM, holding 2048 bits as 256 words of 8 bits, erased by ultraviolet light through a quartz window.
3. That erase uses light at 253.7 nm, typically for 20 to 30 minutes. Ordinary glass blocks that wavelength, which is why the window had to be quartz.
4. EEPROM based on Fowler-Nordheim tunnelling was patented by Siemens in 1974. Intel’s 2816, a 16 kilobit EEPROM developed by a team including George Perlegos, arrived in 1978.
5. Fujio Masuoka invented flash at Toshiba in 1980. NOR flash was presented in 1984 and NAND flash at the IEEE International Electron Devices Meeting in San Francisco in 1987. Intel shipped the first commercial NOR flash in 1988.
6. NOR gives random byte-level read and is used for boot code executed in place. NAND is read and written a page at a time and erased a block at a time.
7. Since Samsung’s V-NAND in 2013, NAND has been built vertically. Layer counts passed 200 in 2022 and current products sit in the 200 to 300 plus range. Stacking, not lithographic shrinking, is now the density driver.
8. Retention is standardized. JEDEC JESD218 requires a client SSD to hold data 1 year at 30 degrees Celsius and an enterprise SSD 3 months at 40, at the end of rated endurance. Fresh cells do far better.
9. Embedded MRAM has replaced embedded flash at 22 nm and below at TSMC, Samsung and GlobalFoundries, because flash cell physics does not scale below about 28 nm.
10. Tools that observe this: smartctl -a /dev/nvme0 and nvme smart-log report NAND wear as percentage used, and flashrom reads and writes NOR devices.

WORDS6.10.6 remember these#

1. Mask ROM — bits built in at the factory — contents fixed by a photomask layer during fabrication.
2. PROM — write once, never again — one-time programmable memory using fusible links or antifuses.
3. EPROM — erasable by ultraviolet light — floating-gate memory in a package with a quartz window, erased in bulk.
4. EEPROM — erasable by voltage, byte by byte — electrically erasable floating-gate memory using tunnelling.
5. Flash — EEPROM that erases in big blocks — block-erasable floating-gate or charge-trap memory, NOR or NAND organized.
6. Floating gate — an island of conductor holding electrons — an isolated gate in the oxide that shifts the transistor threshold voltage.
7. Tunnelling — electrons crossing a barrier they should not — Fowler-Nordheim conduction through thin oxide under a high field.
8. Endurance — how many rewrites it survives — rated program and erase cycles before the oxide degrades out of specification.

6.11 Memory as a grid: addresses, word lines and bit lines#

PLAIN6.11.1 in simple words#

1. A memory chip is a rectangle of cells laid out in rows and columns.
2. Horizontal wires run across the rows. Each is a word line, and raising one selects that whole row.
3. Vertical wires run down the columns. Each is a bit line, carrying one cell’s value in or out.
4. An address is a number saying which cell or group of cells you want.
5. The circuit that turns an address into exactly one raised word line is the address decoder.
6. A decoder with n inputs selects 2 to the power n rows, because n binary digits make that many patterns.
7. So with n address lines you reach 2 to the power n locations, and to reach L locations you need n equal to the base-2 logarithm of L, rounded up.

PLAIN6.11.2 a picture in your head#

1. A block of post office boxes arranged in a grid on a wall.
2. Every box has a number, and that number is the address.
3. A clerk takes the number, walks to one row, then along it to one box.
4. The decoder is the clerk. Number in, one box selected, nothing else.
5. The clerk does not read the letter. Reading is a separate job done by the sense amplifiers on the bit lines.

Where this comparison breaks:

1. A clerk walks, so distant boxes take longer. A decoder is a tree of gates and takes the same time for any address. That is exactly what “random access” means: every location costs the same.

PLAIN6.11.3 a worked example#

                bit 0        bit 1        bit 2
                  |            |            |
  word line 0 ----C------------C------------C----
                  |            |            |
  word line 1 ----C------------C------------C----
                  |            |            |
  word line 2 ----C------------C------------C----
                  |            |            |
              [sense amp]  [sense amp]  [sense amp]
                  |            |            |
                     column select logic
                            |
                        data out

1. Forward. How many locations can 16 address lines reach? Two to the power 16 is 65 536.
2. Backward. How many lines does a 1 gibibyte byte-addressable memory need? One gibibyte is 2 to the power 30 bytes, so 30 lines.

3. Every doubling of capacity costs exactly one more address line.
4. A historical note this explains. The original IBM PC used an Intel 8088 with 20 address lines, reaching 2 to the power 20 bytes, which is 1 MiB. That is where the famous 640 KiB usable limit came from, once the top 384 KiB was reserved.

PLAIN6.11.4 what is really happening inside#

1. A decoder with 20 inputs and a million outputs, built directly, would be absurd. Real designs never do that.
2. First trick, split the address: some bits pick a row, the rest pick a column within the row.
3. A one megabit array becomes 1024 rows by 1024 columns, needing one 10-to-1024 row decoder and one 10-to-1024 column selector.
4. That is also why arrays are roughly square. A square minimizes total wire length, and wire length is delay.
5. Second trick, predecoding: decode in two stages, for instance two 5-to-32 decoders whose outputs are combined in pairs.
6. Third trick, used in DRAM: send row bits and column bits down the same pins at different times. That is the RAS and CAS scheme of section 6.9, halving the address pins.
7. Real chips also carry spare rows and columns. If test finds a bad one, fuses redirect its address to a spare, so almost every memory chip you have used contains repaired defects.

TECHNICAL6.11.5 the engineer’s version#

1. An n-to-2-to-the-n decoder asserts exactly one output per input code. Built flat it needs 2 to the power n gates of n inputs each, so it is always built hierarchically, with predecoding feeding NAND word line drivers.
2. Array organization is quoted as rows by columns by bits per word, plus a column multiplexer ratio. A 4:1 column mux means four bit line pairs share one sense amplifier, trading speed for area.
3. Sub-arrays, called mats, keep word lines and bit lines short. A large cache is dozens of mats with hierarchical decoding. The academic tool CACTI models exactly this trade-off.
4. Cache address terminology is the same grid indexed cleverly: low bits are the byte offset in a line, middle bits are the set index driving the decoder, high bits are the tag that is compared.
5. Redundancy repair uses laser fuses or electrical antifuses set at wafer test. DDR4 and DDR5 also support post-package repair, retiring a failing row in the field.
6. The formulas worth memorizing:

   locations      = 2 ** address_lines
   address_lines  = ceil(log2(locations))
   total_bits     = locations * word_width

7. Tools that observe this: lsmem and /proc/iomem show the physical address layout on Linux, and cpuid reports the physical address width a processor implements, commonly 46 to 52 bits rather than the full 64.

WORDS6.11.6 remember these#

1. Address — the number naming a location — a binary code decoded to select one row and one column of an array.
2. Address decoder — turns a number into one selected row — an n-to-2-to-the-n selector, built with predecoding.
3. Word line — the horizontal select wire — the row line driven high to connect a row of cells to their bit lines.
4. Bit line — the vertical data wire — the column line carrying charge or current between a cell and a sense amplifier.
5. Random access — every location costs the same — access latency independent of the address, unlike tape or a spinning disk.
6. Redundancy repair — spare rows replacing broken ones — fuse or antifuse remapping of failing addresses to redundant elements.

6.12 Volatile, non-volatile, and memory versus storage#

PLAIN6.12.1 in simple words#

1. Volatile means the contents vanish when power goes. SRAM and DRAM are volatile.
2. Non-volatile means they survive. Flash, ROM and disks are non-volatile.
3. That is a property of the cell, and it is not the same as the difference between memory and storage, though people mix the two up constantly.
4. Memory is what the processor reaches directly, one byte at a time, with ordinary load and store instructions.
5. Storage is what it reaches by asking a device to move a block, through operating system calls like read and write.
6. The real dividing line is how the processor talks to it, not whether it forgets.
7. Memory is measured in nanoseconds. Storage is microseconds for an SSD and milliseconds for a spinning disk.
8. The line is genuinely blurring, because some devices are non-volatile yet sit on the memory bus and are addressed a byte at a time.

PLAIN6.12.2 a picture in your head#

1. Memory is the desk you work at. Storage is the filing cabinet in the corner.
2. Anything on the desk you touch instantly, without asking anyone.
3. Anything in the cabinet you must fetch, and you fetch a whole folder, not one line of one page.
4. At the end of the day the cleaners clear the desk and leave the cabinet.
5. Persistent memory is a desk the cleaners have been told to leave alone. Still a desk, with desk speed and desk habits, but it survives the night.

Where this comparison breaks:

1. A desk that survives the night sounds purely good. It creates a hard new problem: if power fails halfway through an update you are left with a half-updated permanent structure, and most programs are not written for that.

PLAIN6.12.3 a worked example#

1. Watch what happens when you save a file.
2. Your editor holds the text in DRAM: fast, byte-addressable, gone if power drops.
3. You press save, and the operating system copies the bytes into a page cache, still in DRAM.
4. It then issues a block write to the SSD, whose controller collects it into a page and eventually programs it into NAND cells.
5. Only after that program completes is the data non-volatile.
6. Lose power between steps 3 and 5 and the file is lost, even though the save appeared to succeed. That is why fsync exists and why databases care about it so much.
7. With persistent memory on the memory bus the sequence is shorter: a store instruction plus a cache line flush and a fence makes the data durable, with no block layer at all.

PLAIN6.12.4 what is really happening inside#

1. Byte-addressable means the address bus can name any single byte, and load and store instructions work on it directly.
2. Block-addressable means the smallest unit that can move is a sector or page, historically 512 bytes and now usually 4096.
3. That difference is not a detail. It is why file systems, page caches, drivers and interrupt handling exist at all.
4. Non-volatile memory on the memory bus removes that stack. You map the device into your address space and use pointers.
5. The catch is the CPU caches. A store lands in a cache, not in the persistent device, and until it is flushed out it is still volatile.
6. So persistent memory programming needs explicit instructions to push cache lines out and to order those pushes.
7. The honest version: both “persistent memory is just fast storage” and “it is just memory that survives” are wrong. It is a third thing, with the addressing of memory and the durability rules of storage.

TECHNICAL6.12.5 the engineer’s version#

1. The three-way comparison, with figures for August 2026:

2. Read the cost row carefully. SRAM is never sold by the gigabyte, so that figure is an estimate from silicon area and public wafer price estimates, as worked out in section 6.8.
3. The DRAM figure must be dated. TrendForce reported conventional DRAM contract prices up 90 to 95 per cent in the first quarter of 2026. Retail DDR5 in August 2026 was 16 to 18 US dollars per gigabyte, against 2 to 4 before.
4. The NAND figure is a drive-level price, around 76 US dollars per terabyte for consumer Gen 4 NVMe in mid 2026, including controller, cache and packaging. Raw NAND is cheaper.
5. So the ratios matter more than the absolute numbers. SRAM to DRAM is roughly ten to one, and DRAM to NAND roughly two hundred to one. Those ratios have been broadly stable for two decades, and they are why the memory hierarchy has the shape it does.
6. Persistent memory history, told honestly. Intel and Micron announced 3D XPoint in July 2015. Intel shipped it as Optane DC Persistent Memory in DIMM form from April 2019 and announced the wind-down of the Optane business in July
   2022. The product is discontinued. The idea is not.
7. NVDIMM-N remains available: ordinary DRAM plus flash plus a supercapacitor, copying DRAM to flash on power loss. It is byte-addressable at DRAM speed and persistent across power cuts.
8. CXL, Compute Express Link, attaches memory over a PCI Express physical layer. CXL 2.0 arrived in 2020, 3.0 in 2022 and 3.1 in late 2023. Expanders add capacity at 150 to 250 ns rather than a local DIMM’s 80 ns.
9. Persistent memory programming uses the x86 CLWB and CLFLUSHOPT instructions with SFENCE, and on Linux the DAX mode of ext4 and xfs with the ndctl and daxctl tools.
10. Where experts disagree: whether byte-addressable persistence will become mainstream. One camp points to Optane’s commercial failure. The other points to CXL, to embedded MRAM shipping in volume, and to the argument that the software problem, not the device, was Optane’s real barrier.

WORDS6.12.6 remember these#

1. Volatile — forgets without power — state maintained only while the supply rail is present.
2. Non-volatile — remembers without power — state held by trapped charge, magnetization or physical structure.
3. Memory — what the processor reaches directly — byte-addressable storage on the load-store path, latency in nanoseconds.
4. Storage — what the processor asks a device for — block-addressable media behind a controller and a driver stack.
5. Persistent memory — non-volatile but used like memory — byte-addressable non-volatile media mapped into the address space.
6. CXL — a newer way to hang memory off a processor — Compute Express Link, a cache-coherent protocol layered on PCI Express.

6.98 Common wrong ideas#

1. Wrong: a latch and a flip-flop are the same thing. Right: a latch is transparent while its enable is active, a flip-flop samples only at an edge.
2. Wrong: a flip-flop stores whatever is on D while the clock is high. Right: it stores what was on D during the setup window before the edge.
3. Wrong: metastability is a bug a good engineer avoids. Right: it is a physical certainty at any asynchronous boundary, and the only defence is buying settling time to make it astronomically rare.
4. Wrong: two flip-flops in a synchronizer guarantee correctness. Right: they give a long MTBF for one bit. Multi-bit crossings still need Gray coding, a handshake or a FIFO.
5. Wrong: a faster clock always means a faster machine. Right: useful work per cycle is set by logic depth, and roughly 15 to 20 gate delays per cycle has been near constant for two decades.
6. Wrong: DRAM refresh is like topping up a battery. Right: refresh is a full read and rewrite of a row through the same sense amplifiers as a normal read, because reading DRAM destroys the stored charge.
7. Wrong: DRAM has got much faster over the years. Right: bandwidth rose about sixteenfold from DDR-400 to DDR5-6400 while CAS latency improved only from about 15 ns to about 12.5 ns.
8. Wrong: RAM is memory and an SSD is storage because one forgets and one does not. Right: the line is byte-addressable load and store versus block transfer. Persistent memory is non-volatile and is still memory.
9. Wrong: flash stores bits in tiny capacitors like DRAM. Right: flash shifts a transistor’s threshold voltage using charge trapped on an isolated gate or in a nitride layer, and needs no power to hold it.
10. Wrong: SRAM is faster because it sits closer to the CPU. Right: it is faster because the value is already held by a driven inverter pair, so there is no charge sharing, sensing or restore step.

6.99 Chapter summary in 20 lines#

1. A logic gate has no past. Its output depends only on its inputs right now.
2. Wiring an output back to an input creates feedback, and feedback creates two stable resting states. That is one stored bit.
3. Two cross-coupled inverters are the ancestor of every memory cell, back to the Eccles-Jordan trigger circuit of 1918.
4. Two cross-coupled NOR gates give the SR latch, with set, reset, hold and one forbidden combination.
5. Generating S and R from a single D input removes the forbidden case and gives the gated D latch, transparent while enabled.
6. Transparency is a hazard, because data can race through several stages inside one enable pulse.
7. Two latches on opposite clock phases give a master-slave D flip-flop, which samples once per edge and cannot be raced through.
8. A flip-flop needs D steady for a setup time before the edge and a hold time after it, from tens of nanoseconds in 1970s TTL to tens of picoseconds today.
9. Violating that window can leave the output hovering between 0 and 1. That is metastability, and it can be made rare but never removed.
10. MTBF rises exponentially with settling time, which is why one extra flip-flop in a synchronizer moves the answer by many orders of magnitude.
11. The clock is a square wave whose rising edge makes the whole chip take one step together, distributed through a buffered tree.
12. Clock skew, jitter and the tree’s own power are the costs of marching in step, and clock gating is the first way to cut that power.
13. Flip-flops side by side make a register, chained make a shift register, and with next-value logic make a counter.
14. Synchronous counters update every bit on one edge. Ripple counters are cheaper and briefly show values nobody intended.
15. A state register plus next-state logic plus output logic is a finite state machine, Moore if outputs depend on state alone, Mealy if on inputs too.
16. A CPU control unit is exactly that, only larger, and since Wilkes proposed microprogramming in 1951 much of it has lived in microcode.
17. SRAM holds a bit in six transistors as a live inverter loop, so it is fastest and dearest per bit and is used for registers and caches.
18. DRAM holds a bit as about 69 000 electrons on a tiny capacitor. It is dense and cheap, it leaks, it must be refreshed within 64 ms for DDR4 or 32 ms for DDR5, and reading it destroys it.
19. Flash holds a bit as charge trapped on an isolated gate, placed and removed by tunnelling or hot-electron injection, surviving years without power at the cost of limited rewrite endurance.
20. Every memory is a grid of word lines and bit lines behind a decoder, n address lines reach 2 to the power n locations, and memory differs from storage by byte-addressing, not by volatility.